This invention relates generally to charge pumps, their design and operation, and to use of such charge pumps in circuits including Phase Locked Loops (PLLs).
Charge pumps are used in a variety of integrated circuits for a variety of purposes. For example, certain PLLs use a charge pumps stage. PLLs are used in a variety of applications in various integrated circuits including memory systems, controllers, programmable logic systems, and others.
FIG. 1 illustrates phase-locked loop (PLL) circuitry, according to the prior art. A phase-frequency detector (PFD) generates an input to a charge pump (CP). The input consists of an up signal (“UP”) and a down signal (“DN”) in this example. This output is generated by comparing the phase difference of a reference signal (“Ref_clk”) to a feedback signal (“Fbk_clk”). The PFD outputs the up signal and the down signal depending on whether or not the phase of the feedback signal lags (needs to speed up) or leads (needs to slow down) when compared to the input signal. The charge pump generates current pulses in a charge pump output signal (e.g., to charge capacitors in loop filter circuitry) based on the up signal and the down signal.
The loop filter circuitry filters the charge pump output signal and generates a filtered control signal. Voltage controlled oscillator (VCO) generates an output signal whose frequency (Fout) is determined by the voltage of the filtered charge pump output. The PLL loops the output signal back to the PFD. A frequency divider circuitry may be placed in the feedback path of the loop to allow the output signal to be a multiple of the input signal (this is optional).
FIG. 2 shows a simplified schematic of a charge pump such as the charge pump of FIG. 1. Two inputs, “UP” and “DN” are received from the PFD and drive up and down switches respectively to connect an output node to one of two current sources, an up-current source (providing current Iup) and a down-current source (providing current Idn), which charge and discharge the output node respectively. The charge pump generates an output from the output node which lies between the up switch and the down switch. The up and down switches that provide the output from the UP and DN signals may be considered to be the charge pump core (indicated by the dashed line in FIG. 2).
In one mode, the UP and DN signals direct the up switch to open and the down switch to close. Because the down switch is closed, the down-current source is electrically connected to the output node through a low-resistance path and removes charge from the output node so that the output voltage drops. This may be considered a discharging mode of the charge pump core. In another mode, the UP and DN signals direct the up switch to close and the down switch to open. Because the up switch is closed, the up-current source is electrically connected do the output node through a low-resistance path and adds charge to the output node so that the output voltage increases. This may be considered a charging mode of the charge pump core.
One non-ideal charge pump characteristic that may occur is current mis-matching. For proper operation of a charge pump, the current that is produced by the up-current source, Iup, should exactly match the current that is produced by the down-current source, Idn, for all conditions. If these currents are not always equal, the charge on the output node and therefore the voltage on the output node will either rise faster or slower than expected, leading to non-linear behavior such as phase error and/or jitter.
Thus, there is a need for a charge pump that provides matched charging and discharging currents to a charge pump core throughout a range of conditions.